Latest VHDL MCQs – Data Types, Operators and Attributes ( VHDL ) MCQs
Latest VHDL MCQs
By practicing these MCQs of Data Types, Operators and Attributes ( VHDL ) MCQs – Latest Competitive MCQs , an individual for exams performs better than before. This post comprising of objective questions and answers related to “ Data Types, Operators and Attributes ( VHDL ) Mcqs “. As wise people believe “Perfect Practice make a Man Perfect”. It is therefore practice these mcqs of VHDL to approach the success. Tab this page to check ” Data Types, Operators and Attributes ( VHDL )” for the preparation of competitive mcqs, FPSC mcqs, PPSC mcqs, SPSC mcqs, KPPSC mcqs, AJKPSC mcqs, BPSC mcqs, NTS mcqs, PTS mcqs, OTS mcqs, Atomic Energy mcqs, Pak Army mcqs, Pak Navy mcqs, CTS mcqs, ETEA mcqs and others.
VHDL MCQs – Data Types, Operators and Attributes ( VHDL ) MCQs
The most occurred mcqs of Data Types, Operators and Attributes ( ) in past papers. Past papers of Data Types, Operators and Attributes ( VHDL ) Mcqs. Past papers of Data Types, Operators and Attributes ( VHDL ) Mcqs . Mcqs are the necessary part of any competitive / job related exams. The Mcqs having specific numbers in any written test. It is therefore everyone have to learn / remember the related Data Types, Operators and Attributes ( VHDL ) Mcqs. The Important series of Data Types, Operators and Attributes ( VHDL ) Mcqs are given below:
Data Objects and Types
1. SIGNED and UNSIGNED data types are defined in which package?
a) std_logic_1164 package
b) std_logic package
c) std_logic_arith package
d) standard package
Answer: c
Explanation: SIGNED and UNSIGNED data types are defined in the std_logic_arith package of the IEEE library. These data types are mainly intended for arithmetic operations. This is why they are defined in the arithmetic package.
2. What is the correct method to declare a SIGNED type signal ‘x’?
a) SIGNAL x : IN SIGNED
b) SIGNAL x : IN SIGNED
c) SIGNAL x : IN SIGNED (7 DOWNTO 0)
d) SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0)
Answer: c
Explanation: Unlike BIT and STD_LOGIC types; SIGNED and UNSIGNED follow the syntax similar to BIT_VECTOR and STD_LOGIC_VECTOR. Also, IN and OUT are just to specify the direction of signal.
3. An UNSIGNED type is always greater than zero.
a) True
b) False
Answer: a
Explanation: In SIGNED and UNSIGNED, SIGN word refers to the positive or negative sign of any number. UNSIGNED data type has no sign and therefore, it is always positive. Therefore, an UNSIGNED number will be always greater than zero.
4. What will be the value of x in the following code?
SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;
a) 12
b) 5
c) -5
d) 14
Answer: d
Explanation: x is declared as an UNSIGNED data type. Therefore, all the 4 bits will be data bits and it will be positive. So, converting 1101 in decimal, we get 1101 equivalent to 14 in decimal number system.
5. What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 ); x <= “1101”;
a) -5
b) 5
c) -3
d) -14
Answer: c
Explanation: Signed numbers always have first bit representing the sign of the number which is one for the negative and zero for the positive. Also, signed number is represented in 2’s complement form. Therefore, the given number is -3.
6. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?
a) x <= a + b; y <= a – b;
b) x <= a OR b; y <= a AND b;
c) x <= a + b; y <= a OR b;
d) x <= a OR b; y <= a + b;
Answer: a
Explanation: SIGNED and UNSIGNED data types are intended for arithmetic operations mainly and using logical operators with these data types is illegal. Therefore, only option x <= a + b; y <= a – b; is completely legal. In all other options there are logical operations so those can’t be considered as legal.
7. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?
a) x <= a.b
b) x <= a OR b
c) x <= a + b
d) x <= a && b
Answer: b
Explanation: Unlike SIGNED and UNSIGNED, STD_LOGIC_VECTOR data type is used mainly for logical operations and we can’t use arithmetic operations with STD_LOGIC_VECTOR. Also, && is not the sign for any operation in VHDL, if you want to perform and operation, then you have to write AND not &&.
8. What do we call the data type used for representing distance, current, voltage, time, etc?
a) Integer
b) Real
c) Physical
d) Imaginary
Answer: c
Explanation: Physical type is used for representing physical values such as time, voltage, etc. by using some base unit. Physical quantities are used in various digital systems and these are important for modelling such systems. Integer and Real are the data types for numbers and there is no data type called Imaginary.
9. What is the meaning of the base unit?
a) Smallest possible unit of any physical literal
b) SI unit of any physical literal
c) CGS unit for any physical literal
d) Fundamental building block of any design
Answer: a
Explanation: Base unit is the smallest possible unit for any physical literal by using which we can derive all other units of the same literal. For example, in case of TIME, the base unit is nanosecond. We can create any bigger unit by using nanoseconds. For example 1 microsecond = 1000 nanosecond.
10. Which of the following is only predefined physical literal in VHDL?
a) VOLTAGE
b) TIME
c) CURRENT
d) DISTANCE
Answer: b
Explanation: TIME is the only predefined physical data type in VHDL. The base unit of TIME is nanosecond. TIME literal is defined in the standard package of std library.
11. SIGNAL a : REAL; which of the following is illegal assignment for a?
a) a <= 1.8
b) a <= 1.0 E10
c) a <= 1.0 E-10
d) a <=1.0 ns
Answer: d
Explanation: Units nanosecond (ns) written after the number shows that it is of type TIME and VHDL doesn’t allow TIME type to be assigned to a real Signal. So option d is illegal.
12. Multidimensional arrays can be used for the implementation of memories.
a) True.
b) False.
Answer: a
Explanation: Multidimensional arrays can be seen as array of arrays. For example, we need to implement ROM of 512×4 then we need to define a 2 dimensional array with 4 columns and 512 rows. So, memories can be defined by using 2D array. In which one dimension can show the size of memory and another can show the width of one word.
13. RECORD in VHDL is similar to________ in C.
a) Array
b) File
c) Structure
d) Pointer
Answer: c
Explanation: As in C, Structures are used to collect different data types under a common name. Similarly, RECORD type in VHDL is used for collecting different data types and objects in a single object.
14. What is the difference between SIGNAL and VARIABLE?
a) The value of SIGNAL never varies whereas VARIABLE can change its value
b) SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
c) SIGNAL depends upon VARIABLE for various operations
d) SIGNAL is global and VARIABLE is local to the process in which it is declared
Answer: d
Explanation: SIGNALs are used to pass information between entities, they act as interconnection between different entities whereas VARIABLEs can be used in the process or subprogram in which it is declared. So, VARIABLEs are local to the block in which they are declared.
15. Access types are similar to _________ in traditional programming languages.
a) Pointers
b) Arrays
c) Structures
d) Files
Answer: a
Explanation: Access types are used to hold an address of some object which is quite similar to pointers in traditional programming languages. By using the address stored in Access data type, we can access another data objects similar to pointers.
User defined Data Types
1. How the keyword “TYPE” is used?
a) TYPE datatype_name IS type_from_predefined_datatypes;
b) TYPE datatype_name IS datatype_range;
c) TYPE datatype_range IS datatype_name;
d) USE TYPE datatype_range IS datatype_name;
Answer: b
Explanation: The keyword TYPE is used to define new data type if any user wants to define for its own. The syntax for keyword is- TYPE datatype_name IS datatype_range. So, the new data type can have the values defined in range section of the declaration.
2. Which of the following is a wrong declaration for a new data type?
a) TYPE my_logic IS RANGE 0 to 100;
b) TYPE my_logic IS (‘0’, ‘1’, ‘2’);
c) TYPE my_logic IS ARRAY (0 TO 3) OF BIT;
d) TYPE my_logic IS <0 TO 20 >
Answer: d
Explanation: TYPE can be used in three forms as shown above. For defining range, there are two methods as illustrated in option TYPE my_logic IS RANGE 0 to 100; and option TYPE my_logic IS (‘0’, ‘1’, ‘2’);. If we want to define a user defined array then the sytanx like option TYPE my_logic IS ARRAY (0 TO 3) OF BIT; follows. But, we can’t define range by using <> sign.
3. One can’t define an array without any constraints in VHDL.
a) True
b) False
Answer: b
Explanation: We can define an array without any constraints in VHDL. When there are no constraints in array then it can have any number of elements. For example, TYPE my_type IS ARRAY (RANGE <>) OF BIT; this declaration defines an array of BIT data type without any constraint on the number of elements in the array.
4. A SUBTYPE can be defined as _________
a) A TYPE under a TYPE (nested)
b) A type of INTEGER datatype
c) A TYPE with some constraint
d) A TYPE without any constraint
Answer: c
Explanation: A SUBTYPE is a TYPE with some constraints. TYPE can be predefined data type and it can also be any user defined data type. But if SUBTYPE is derived from user defined datatype, then we first have to declare the type along with its range and then subtype can be defined.
5. Which of the following is the correct syntax for declaring a SUBTYPE?
a) TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
b) SUBTYPE subtype_name IS subtype_range TYPE type_name
c) SUBTYPE subtype_name TYPE type_name IS subtype_range
d) SUBTYPE subtype_name IS TYPE subtype_range
Answer: d
Explanation: The correct way to define a SUBTYPE is the syntax shown in option d. For example, if we want to define a SUBTYPE of STD_LOGIC with 3 values only like X, 0 and 1. We can define it as SUBTYPE my _ subtype IS STD_LOGIC RANGE ‘X’ TO ‘1’.
6. Which of the following can’t be the value of x? Refer to the VHDL code given below.
TYPE color IS (red, green, blue, black, white, gray);
SUBTYPE primary IS color RANGE red to blue;
VARIABLE x: primary;
a) White
b) Red
c) Green
d) Blue
Answer: a
Explanation: PRIMARY is a subtype of COLOR as declared in the code. The range of PRIMARY is declared “red” to “blue”. It means that an object of Primary type can have values red, green or blue. So White can’t be assigned to x.
7. Look at the following declarations:
TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;
How many total bits can be stored in these arrays?
a) 16
b) 9
c) 64
d) 27
Answer: c
Explanation: First of all, array1 is array of BIT_VECTOR type that means it contains 4 BIT_VECTOR. One BIT_VECTOR is here declared to be consisting of 4 bits. Therefore, Array 1 can have 16 bits. Now, array2 is an array of 4 array1. Therefore, total bits are 4 × 16 = 64.
8. Refer to the four declarations below, which of the following is not a 2 dimensional array?
TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC; TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 ); TYPE array3 IS ARRAY (2 DOWNTO 0 ) OF array2; TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;
a) array4
b) array3
c) array2
d) array1
Answer: b
Explanation: Here, array1 is a 2-D array with 4 rows and 2 columns (3 DOWNTO 0 and 1 DOWNTO 0) of STD_LOGIC type. Though, array2 declaration looks like 1D array, but it is 2D array, since it is of type STD_LOGIC_VECTOR, which is already a 1D array, so array2 is a 2D array. Similarly array4 is 4 × 4 matrix. But, array3 is a 3D array. Because it is 1D array of 2D array named as array2.
9. User can define its own integer data type.
a) True
b) False
Answer: a
Explanation: In VHDL, user can define either its own integer type or enumerated type. User defined integer type must always be a subset of predefined datatype. User can define the integer with some desired range. For example, we can define any integer named as my_integer with range 0 to 32 as given: TYPE my_integer IS RANGE 0 TO 32; in this way, one can define a subset of integer.
10. Which of the following is a SUBTYPE of INTEGER?
a) NATURAL
b) REAL
c) CHARACTER
d) STD_LOGIC
Answer: a
Explanation: We can say that NATURAL is a subtype of INTEGER. The range of NATURAL datatype is 0 to 231-1, whereas the range of INTEGER is – (231-1) to (231-1). Therefore, it can be written as SUBTYPE NATURAL IS INTEGER RANGE 0 TO 2147483647.
Data Conversion
1. Refer to the VHDL code given below, which of the following line has error?
Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;
a) Line 1
b) Line 4
c) Line 5
d) Line 6
Answer: c
Explanation: As a is a SIGNAL of BIT type and b is a SIGNAL of std_logic type; so we can’t perform direct operations on these data. For assigning the value of one data type to another data type, we need to use some type of data conversion. Without data conversion, it is illegal. However, line 6 is legal, because STD_LOGIC and my_logic both has same “base”, which means that my_logic is a subset of STD_LOGIC.
2. One can perform basic operations between different data types.
a) True
b) False
Answer: b
Explanation: VHDL is a strongly typed language i.e. it has very strict rules about predefined and user defined data types. So, we can’t perform any operation between data of different types. Although, it is possible to perform operation between two data types with same base.
3. How to correctly assign the value of 2x+10 to y in the following VHDL code?
TYPE long IS INTEGER RANGE -1000 TO 1000; TYPE short IS INTEGER RANGE -10 TO 10; SIGNAL x : short; SIGNAL y : long;
a) y <= 2*x + 10;
b) long y <= long 2*x + 10;
c) short y <= long (2*x + 10);
d) y <= long (2*x + 10);
Answer: d
Explanation: For all the data types with same base, the conversion can be carried out at the time of operation itself. Therefore, if we want to assign a value of ‘short’ type to a variable of ‘long’ type; we may simply write ‘long’ just after the assignment operator. By doing so, user can convert one type into another. Note that, it is only possible if and only if both the types are having same base.
4. In the VHDL code given below, what will be the error at the time of compilation?
TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2; …
a) Type mismatch
b) Syntax problem
c) No declaration
d) Can’t compile
Answer: a
Explanation: Here, we have two user defined data types which are my_int and other_int with the same base. But, we can’t directly perform any operation between the signals of these two different types. Such kind of error is called “Type Mismatch” error. First, user needs to convert my_int to other_int. so, the correct assignment statement will be:- y<= other_int (x + 2);
5. Which of the following package of IEEE contains most of the data conversion functions?
a) std_logic_1164
b) std
c) std_logic_arith
d) std_logic
Answer: c
Explanation: Most of the conversion functions are defined in the std_logic_arith package of IEEE library. When user need to convert one type of data into another type and both have different bases, then it is essential that he/she need to declare the std_logic_arith package in the library declaration part. However, when we need to convert the data types with same base, then the functions are defined in std_logic_1164 package.
6. If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?
a) STD_LOGIC VECTOR
b) STD_ULOGIC
c) INTEGER
d) SIGNED
Answer: a
Explanation: The function conv_integer(p) is used to convert the parameter ‘p’ of any type excluding STD_LOGIC_VECTOR into the integer type. This function can covert INTEGER, SIGNED, UNSIGNED, STD_ULOGIC types into integer type. After converting only, we can use ‘p’ as INTEGER type.
7. In the function conv_unsigned(p, b), what does p and b refers to?
a) p is the data object to be converted and b is the base of that data object
b) p is the data object to be converted amd b is the bits needed in converted variable
c) p is the parameter to be converted and b is the bits of same parameter
d) p is the type of data to be converted and b is the type of data into which p should be converted
Answer: b
Explanation: The function conv_unsigned is used to convert different data types in UNSIGNED type. Two arguments are used in this function which are p and b. p is the data object which we need to convert and b represents the no of bits in UNSIGNED type. So, conv_unsigned(p,b) converts the parameter ‘p’ of INTEGER, SIGNED, UNSIGNED, STD_ULGOIC into UNSIGNED type of size ‘b’ bits.
8. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?
a) conv_integer_signed(p,b);
b) conv_signed_integer(p,b);
c) conv_signed(p,b);
d) conv_signed_p(b);
Answer: c
Explanation: To convert INTEGER, SIGNED, UNSIGNED and STD_ULOGIC types into SIGNED type, the function conv_signed is used. The correct way to use this function is :- conv_signed(p,b) where p is the object to be converted and b is the number of bits in SIGNED type.
9. The function conv_std_logic_vector(p,b) is used for_______
a) Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type
b) Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits
c) Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits
d) Converting STD_LOGIC into STD_LOGIC_VECTOR
Answer: b
Explanation: This function is used to convert the parameter ‘p’ of type INTEGER, UNSIGNED, SIGNED or STD_LOGIC into STD_LOGIC_VECTOR. Note that the size of converted variable will be ‘b’ bits. So, b represents the number of bits in the converted object.
10. What will be the value of y after the execution of the following VHDL code?
Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8); …
a) 8- bit STD_LOGIC_VECTOR m+n
b) 8- bit UNSIGNED m+n
c) 4- bit STD_LOGIC m+n
d) Error
Answer: a
Explanation: Here, the conversion function is used to convert the data objects into STD_LOGIC_VECTOR type. The operation ‘m+n’ is completely legal since both are UNSIGNED type, after this operation the result is converted into STD_LOGIC_VECTOR with size ‘8’ bits. So, the values assigned to ‘y’ will be of STD_LOGIC_VECTOR type of 8 bits.
11. Refer to the VHDL code given below, what will be the output?
Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL a : IN INTEGER; SIGNAL b : IN UNSIGNED (3 DOWNTO 0); SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); y <<=CONV_STD_LOGIC_VECTOR ((a+b), 8); …
a) 8- bit STD_LOGIC_VECTOR a+b
b) 8- bit UNSIGNED a+b
c) 4- bit STD_LOGIC_VECTOR a+b
d) Error
Answer: d
Explanation: The code is not completely legal. There will be an error of type mismatch. Since a and b are two completely different data types, one is INTEGER and another is UNSIGNED. So, we can’t perform the operation ‘a+b’. Therefore, to perform this operation, first a and b need to be of same type, which can be done by converting INTEGER into UNSIGNED or vice-versa.
Operators – 1
1. Which of the following is not an assignment operator?
a) <=
b) :=
c) =>
d) =
Answer: d
Explanation: Assignment operators are used to assign some value to a data object. <= operator is used to assign values to a SIGNAL. := operator is used to assign values to VARIABLE, CONSTANTS and GENERICS; this operator is also used for assigning initial values. Another assignment operator is =>, used to assign values to individual vector elements or others.
2. A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to assign 1001 to y, then what is the write assignment statement?
a) y <= “1001”
b) y := “1001”
c) y <= ‘1’, ‘0’, ‘0’, ‘1’
d) y => “1001”
Answer: b
Explanation: To assign values to any variable, the := operator is used. Since, y is a VARIABLE STD_LOGIC_VECTOR type, we can only use := operator and not <= operator. => can be used, but while assigning individual elements of a vector.
3. Refer to the VHDL code given below, which is the legal assignment statement?
SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);
a) y <= (1 => ‘1’, OTHERS => ’0’);
b) y := “0100”;
c) y => “0100”;
d) y => x;
Answer: a
Explanation: To assign a value to a SIGNAL, either <= or => can be used only. But, if we want to use =>, then values need to be assigned to individual elements. => is used with OTHERS. Y<= (1<=’1’, OTHERS =>’0’) means that the value assigned to y is 0100.
4. Which of the following logical operator has the highest precedence?
a) NAND
b) NOR
c) NOT
d) EXOR
Answer: c
Explanation: NOT is the logical operator which has highest precedence. If there are more than one logical operator in the same statement, then NOT will be given highest preference. If there is any () in the statement then first preference will be given to () and then to NOT operator.
5. In the following statements, y and z are equivalent to________
y <= NOT a AND b; z <= NOT (a AND b);
a) y <= a’+b’ and z <= (a.b)’
b) y <= (a+b)’ and z <= a’+b’
c) y <= a’+b and z <= a’+b’
d) y <= a+b’ and z <= a.b
Answer: c
Explanation: As discussed above, NOT will be given highest preference. So, y becomes ((NOT a)AND b) which is a’+b. similarly, in z first of all () will be solved i.e.(a AND b)’ which is (a.b)’. By, De Morgan’s law, (a.b)’ = a’+b’. Therefore, y = a’+b and z = a’+b’.
6. Which of the following VHDL statement is equivalent to NAND operation, if y, a and b are SIGNALS?
a) y <= NOT a AND b
b) y <= NOT a OR NOT b
c) y <<= NOT a AND NOT b
d) y <<= NOT (a OR b)
Answer: b
Explanation: Logic NAND operation is (a.b)’ which is equivalent to a’ + b’ by using De Morgan’s law. NOT a AND b is equivalent to (a’.b). NOT a AND NOT b is equivalent to (a’.b’). Similarly, NOT (a OR b) is (a+b)’.
7. ______ operator is unary as well as binary operator.
a) –
b) *
c) /
d) **
Answer: a
Explanation: Unary operator is the one which needs only one operand and Binary operator needs two operands. ‘–’ is the only operator which can be used with one as well as two operands. When used with single operand, the result is negative of the same number and similarly, when used with two operands then the result is difference of two operands.
8. The operator ‘&’ is called the_____ operator.
a) Logical AND operator
b) Bitwise AND operator
c) Arithmetic addition operator
d) Concatenation operator
Answer: d
Explanation: ‘&’ is called the concatenation operator and is a binary operator. It needs two operands and both of them must be arrays. It combines two arrays and produces one array of the size equal to the sum of sizes of two arrays.
9. What is the type of result of MOD operator?
a) Numeric
b) Integer
c) Array
d) Bit
Answer: b
Explanation: The MOD operator is called the modulo operator which gives the remainder of the division of two integers and hence the result is of integer type. For example, y <= a MOD b; will return the value of remainder when a is divided by b. suppose a= 12 and b= 5 then the value of y will be 2.
10. The operators like =, /=, <, >, >= are called _________
a) Arithmetic operators
b) Concatenation operators
c) Logical operators
d) Relational operators
Answer: d
Explanation: These operators are relational operators or Comparison operators since they are used to compare two operands. The = refers to equal to, /= refers to not equal to operator. Similarly,<, >, <=, >= are called less than, greater than, less than or equal to, greater than or equal to operators.
11. What is the type of result for comparison operators?
a) Boolean
b) Integer
c) Numeric
d) Array
Answer: a
Explanation: Comparison operators are used for the comparison of two operands and the result is of Boolean type i.e. true or false. For example, b:= “0010” < “0001”; In this statement, the value assigned to b will be FALSE, since this means 2 < 1, which is not true.
12. ABS operator is used to _________
a) Shift the operand
b) Gives absolute value for the operand
c) Give the result as nearest integer
d) To synthesize the result
Answer: b
Explanation: ABS operator is a unary operator which returns the absolute value. We can use this operator to increase the reliability of code. For example, we need to use π, then the value of the same is 22/7 or 3.14. In VHDL, if we use following statements: pi = 22/7; IF(pi = 3.14) THEN WAIT; Then we might not get the result as we want. It will be unreliable. If we use ABS operator along with it, then it will be better. Like, IF(abs(pi)=3.14) THEN WAIT; this will give the desired result.
13. Which of the following is exponentiation operator?
a) ^
b) *
c) /=
d) **
Answer: d
Explanation: Exponentiation operator in VHDL is represented by two asterisk signs. So, ** is the exponentiation operator which comes under the category of arithmetic operators. In VHDL, a**b means a^b.
Operators – 2
1. SIGNAL x : STD_LOGIC; In this statement x is ______
a) Variable
b) Identifier
c) Name
d) Literal
Answer: b
Explanation: Identifier is a simple name given to any constant, variable, signal, entity, port or a subprogram. A name must begin with alphabetic letter. It may contain alphanumeric characters and underscore sign. Reserved words of VHDL can’t be used as identifiers.
2. What is the use of shift operators?
a) To shift the data
b) To shift the identifiers
c) To shift the operators
d) To shift the STD_LOGIC_VECTOR
Answer: a
Explanation: Shift operators are used to shifting of data. These operators were introduced in the VHDL93.
3. What is the “SLL” operator?
a) Shift Logic Left
b) Shift Logically
c) Shift Left Logical
d) Shift Left
Answer: c
Explanation: SLL is a shift operator used to shift bits of the operand to one left position and fills the rightmost position with zero. Shift Left Logical(SLL) operator will shift the bits logically. For example, we had data 0100 in the operand, then after applying SLL, we will get 1000.
4. The correct syntax for any logical shift operator like SLL and SRL is_____
a) bit_vector_operand <OPERATOR> integer_operand
b) integer_operand <OPERATOR> bit_vector_operand
c) std_logic_operand <OPERATOR> integer_operand
d) integer_operand <OPERATOR> std_logic_operand
Answer: a
Explanation: SLL and SRL operators can shift the operands of vector type. It may be BIT_VECTOR type or STD_LOGIC_VECTOR type. The left operand is shifted towards left or right depending on the operator with number of shifts represented by right operand which always must be an INTEGER type.
5. Refer to the VHDL code given below, what should be the output of the identifier ‘y’ and ‘z’?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x SRL 2; z := x SLL 2; …
a) y = 0100 and z = 0100
b) y = 0010 and z = 0100
c) y = 0100 and z = 1000
d) y = 0010 and z = 1000
Answer: d
Explanation: SRL operator will shift the operand towards right and SLL will shift the same towards left. All the left bits will be filled with zero in SRL operation and in SLL right bits will be filled with zero. Therefore, y must be x shifted towards right with 2 positions.
6. In the following VHDL code, the values of y and z are _____
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x SRA 2; z := y SLA 2; …
a) y = 0000 and z = 0000
b) y = 1001 and z = 0000
c) y = 1110 and z = 0111
d) y = 0111 and z = 1110
Answer: c
Explanation: SRA and SLA expands to Shift Right Arithmetically and Shift Left Arithmetically respectively. These operators shift the left operand towards right or left by number of bits specified by right operand. Unlike SLL and SRL, the empty bits are not filled with zero, but they are replaced with the MSB in case of SRA and with LSB in case of SLA. For example, in above code, if we shift the x towards right arithmetically then it will become 1100, i.e. the MSB is replicated instead of zero. Therefore, Shifting to two positions will give y = 1110 and z= 0111.
7. SLL operation is equivalent to which of the following operations?
a) Multiplication by any natural number
b) Multiplication by 2
c) Division by 2
d) Exponential operation
Answer: b
Explanation: Shift Left Logical shifts the bits towards left and Shift Right Logical shifts towards right. In binary number system, shifting left refers to multiplication with two and similarly, shifting right refers to division by two. For example, the number 0010 represents 2 in decimal number system. Now, if we shift it left by one position then it will become 0100 which is equivalent to 4 in decimal number system. Therefore, shifting left is equivalent to multiplication operation.
8. Which of the following is equivalent division by 2 operator?
a) SRL
b) SLL
c) SLA
d) SRA
Answer: a
Explanation: SRL operator shifts the given operand towards right. For, example, if we have a number 0010, equivalent to two, which is shifted right then it will become 0001 which is equivalent to 1. Therefore, this operation corresponds to division of any number by two.
9. In the VHDL code given below, what will be the values of y and z?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; … y := x ROR 2; z := y ROL 2; …
a) y = 0100 and z = 0000
b) y = 0000 and z = 0000
c) y = 0111 and z = 1110
d) y = 0110 and z = 0110
Answer: d
Explanation: ROR and ROL are Rotate Right and Rotate Left operators respectively. These operators’ wraps around the operand that means the bit shifted out will replace the vacant bit. Therefore, Rotating x two times towards right will give 0110 in y and when it is rotated left then it will be the same.
10. In a statement containing two or more operators of same precedence, how the expression will be solved?
a) Left to right
b) Right to left
c) Alphabetically
d) In a random manner
Answer: a
Explanation: In VHDL, to solve any expression a simple rule is followed. The rule is “highest precedence first, left to right within same precedence”. However, we can use parenthesis to control the order of operations, but by default it will solve left to right. It may be noted that parenthesis is the operator with highest precedence.
11. What will be the values of the following variables after MOD operations?
x = 5 MOD 3; y = -5 MOD 3; z = 5 MOD -3;
a) x = 2, y = -2 and z = -2
b) x = 2, y = 1 and z = -2
c) x= 2, y = -2 and z = 2
d) x = 2, y = -2 and z = 1
Answer: b
Explanation: MOD takes the sign of divisor which is the second operand, but not of first operand. In the first operand, it will simply give the remainder which is 2. In the second statement, the modulo will not contain negative, it will simply divide and the result will be 1. This is done by adding 3*2 in -5, in that case 1 is left, therefore modulo is 1. But, in third statement, divisor is negative so it will be taken as -(5 MOD 3).
12. What will be the values of following variables after REM operations?
x = 5 REM 3; y = -5 REM 3; z = 5 REM -3;
a) x= 2, y = 1 and z = -2
b) x = 2, y = -2 and z = 1
c) x = 2, y = -2 and z = 2
d) x = 2, y = 1 and z = 1
Answer: c
Explanation: Here, REM operator is used, which takes the sign of dividend instead of divisor unlike MOD operator. In case of negative divisor, the sign is ignored. Therefore, in first statement, the remainder is calculated normally, which is 2. In second statement, it will be considered as -(5 REM 3). In third statement, it is simply solved like first statement, ignoring the negative sign.
13. XNOR is a logical operator in VHDL.
a) True
b) False
Answer: a
Explanation: XNOR is a logical operator representing Ex-NOR operation and was introduced in VHDL 93. In the previous versions, there was no XNOR operator and to perform Ex-NOR, we needed to implement it by using XOR itself.