Up To Date Introduction to VHDL ( VHDL ) MCQs – VHDL MCQs

Latest VHDL MCQs

By practicing these MCQs of Introduction to VHDL ( VHDL ) MCQs – Latest Competitive MCQs , an individual for exams performs better than before. This post comprising of objective questions and answers related to “ Introduction to VHDL ( VHDL ) Mcqs “. As wise people believe “Perfect Practice make a Man Perfect”. It is therefore practice these mcqs of VHDL to approach the success. Tab this page to check ” Introduction to VHDL ( VHDL )” for the preparation of competitive mcqs, FPSC mcqs, PPSC mcqs, SPSC mcqs, KPPSC mcqs, AJKPSC mcqs, BPSC mcqs, NTS mcqs, PTS mcqs, OTS mcqs, Atomic Energy mcqs, Pak Army mcqs, Pak Navy mcqs, CTS mcqs, ETEA mcqs and others.

VHDL MCQs – Introduction to VHDL ( VHDL ) MCQs

The most occurred mcqs of Introduction to VHDL ( ) in past papers. Past papers of Introduction to VHDL ( VHDL ) Mcqs. Past papers of Introduction to VHDL ( VHDL ) Mcqs . Mcqs are the necessary part of any competitive / job related exams. The Mcqs having specific numbers in any written test. It is therefore everyone have to learn / remember the related Introduction to VHDL ( VHDL ) Mcqs. The Important series of Introduction to VHDL ( VHDL ) Mcqs are given below:

EDA Tools

1. What is the full form of VHDL?
a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language
Answer: d
Explanation: Most people confuse Verilog Hardware Description Language with VHDL but, VHDL means VHSIC Hardware Description Language where VHSIC is the acronym for Very High Speed Integrated Circuits.

2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation
Answer: c
Explanation: EDA expands to Electronic Design Automation and these tools are used for synthesis, implementation and simulation of Electronic circuits on the software itself.

3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
b) FPGA
c) Optimized netlist
d) Netlist
Answer: d
Explanation: After entering the code into any EDA tool, we need to compile the code. When the compilation is complete, then we get the complete netlist of the system designed by using VHDL. After which optimization process is used to optimize the netlist and then by placement and routing we get final Physical device.

4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II
Answer: a
Explanation: Quartus II EDA tool is used for Altera CPLD and FPGA devices. Similarly, Xilinx ISE is used for Xilinx CPLD/FPGA devices. MaxPlus is also an advanced EDA tool for Altera CPLDs. Visual C++ is the compiler for C and C++ languages.

5. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification
Answer: b
Explanation: Synthesis means to generate netlist, i.e. describing the circuit by the relation between inputs and outputs by using logic equations. Simulation is whereas to check the correctness of VHDL code and Optimization is to optimize the netlist; optimization is performed after the synthesis. Verification similarly uses different EDA tool to perform gate level verification.

6. Place and Route EDA tools are used to take the design netlist and implement the design in the device.
a) True
b) False
Answer: a
Explanation: Place and Route tools are used to take the netlist and implement it on the target device by taking various factors into consideration like Timing constraints and some device information.

7. An Antifuse programming technology is associated with _________
a) CPLDs
b) FPGAs
c) SPLDs
d) ASICs
Answer: b
Explanation: Antifuse technology is used to burn the information, from place and route tools, into appropriate fuses in the FPGAs.

8. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators
Answer: d
Explanation: Simulators are the tools which are used at the front end and all other tools are used at the back end.

9. What are the differences between simulation tools and synthesis tool?
a) Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code
Answer: c
Explanation: Simulators test basic logic and working of the circuit described in the code and Synthesis allows to take timing factor and other factors into consideration while simulation.

10. What is the extension of the netlist file; input to the place and route EDA tools?
a) EIDF
b) SDF
c) TXT
d) CPP
Answer: a
Explanation: EDIF and XNF are the netlist files; whereas SDF is the file of timing information.TXT is the extension of a simple text file and CPP is the C++ source file.

Need of HDLs

1. In what aspect, HDLs differ from other computer programming languages?
a) No aspect; both are same
b) HDLs describe hardware rather than executing a program on a computer
c) HDLs describe software and not hardware
d) Other computer programming languages have more complexity
Answer: b
Explanation: HDLs (Hardware Description Languages) are used to describe hardware for any electronic circuit or system; whereas other computer programming languages execute a program on the computer itself.

2. Which of the following HDLs are IEEE standards?
a) VHDL and Verilog
b) C and C++
c) Altera and Xilinx
d) Quartus II and MaxPlus II
Answer: a
Explanation: VHDL and Verilog are the only two HDLs endorsed by IEEE. C andC++ are not HDLs. Altera and Xilinx are devices on which these HDLs can be used. Quartus II and MaxPlus II are the platforms for simulation of hardware described by HDLs.

3. Why we needed HDLs while having many traditional Programming languages?
a) Traditional programming languages are complex
b) HDLs are complementary to traditional programming languages to complete the design process
c) Some characteristics of digital hardware couldn’t be captured by traditional languages
d) HDLs offer more complexity than traditional programming languages.
Answer: c
Explanation: Digital systems are very complex and this complexity is increasing day by day. Some characteristics like propagation delay, concurrent processing and interconnection of parts can’t be captured with traditional languages.

4. An HDL can’t describe Hardware at Gate level as well as switch level?
a) True
b) False
Answer: b
Explanation: An HDL supports the hierarchical design process. It can describe the circuit or hardware at every possible level, whether it is gate level or switch level or RTL level.

5. Why do we need concurrent processing for describing digital systems in HDLs?
a) Faster processing than conventional programming languages
b) Concurrent processing is easier than sequential processing
c) It allows taking timing constraints into consideration
d) Complexity of digital systems needs concurrent processing
Answer: d
Explanation: Due to the complexity of digital circuits, we need to process all the instructions at the same time. For example, current can flow in the two branches at the same time which can affect the output of the system, if sequentially processed.

6. An ASIC can be correctly designed by using programming languages like C or Assembly.
a) True
b) False
Answer: b
Explanation: By using HDL, we specify what we need. We can optimize the circuit by using HDLs. ASIC(Application Specific IC) is a very complex which may consist of millions of transistors. So, we need concurrent execution first of all. Apart from that, we need timing information and other complex features of the digital system too.

7. VHDL is based on which of the following programming languages?
a) ADA programming language
b) C
c) Assembly
d) PHP
Answer: a
Explanation: The syntax and whole structure of VHDL code is based upon ADA programming language whereas Verilog HDL finds its origin from C language.

8. What is the advantage of using VHDL instead of any other HDL?
a) Week typing
b) Based on ADA
c) Portability
d) Easy to code
Answer: c
Explanation: A circuit specified in VHDL can be implemented in different chips and is compatible with CAD tools provided by all companies. Therefore, without any modification, we can use VHDL code anywhere. This is the biggest advantage because digital circuit technology changes rapidly.

9. Which of the following is a characteristic of VHDL?
a) Case sensitive
b) Use of simple data types
c) Based on C programming language
d) Strongly typed language
Answer: d
Explanation: VHDL is a strongly typed language i.e. we have to write a long code to define operations.

10. Which of the following is a characteristic of Verilog HDL?
a) Strongly typed language
b) Case sensitive
c) Better library
d) Not portable
Answer: b
Explanation: Verilog HDL is a case sensitive language which means ‘a’ and ‘A’ means different if you are coding in Verilog.

Common Terms used in VHDL

1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
Answer: b
Explanation: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.

2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Answer: c
Explanation: Package is a collection of all the commonly used data types and subroutines so that programmers can easily use them in their design without defining the same functions again and again.

3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
Answer: a
Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.

4. An entity can have more than one architecture.
a) True
b) False
Answer: a
Explanation: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.

5. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Answer: d
Explanation: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.

6. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
Answer: a
Explanation: Bus is a special kind of signal. It may have its drivers turned off.

7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
Answer: b
Explanation: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.

8. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
Answer: d
Explanation: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.

9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
Answer: c
Explanation: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.

10. A process is the basic unit of execution in VHDL.
a) True
b) False
Answer: a
Explanation: All the operations in the VHDL description are divided into processes during simulation and therefore, Process is the basic unit of execution.

11. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Answer: a
Explanation: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.

12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
Answer: b
Explanation: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.

13. Which of the following is used at the end of a statement?
a) ; (Semicolon)
b) — ( double hyphen)
c) _ (underscore)
d) No sign is used at the end of statement
Answer: a
Explanation: Semicolon is the sign used at the end of any statement. Double hyphen is used for writing a comment which means wherever we have a sign of double hyphen(–), the simulator will skip that line and start compiling from the next line.

14. Which of the following is correctly declared library for VHDL code?
a)

LIBRARY library_name;
USE package_name.parts;

b)

LIBRARY package_name.parts;
LIBRARY library_name;

c)

USE library_name;
LIBRARY library_name.package_name.parts

d)

LIBRARY library_name;
USE library_name.package_name.parts

ENTITY entity_name IS
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END entity_name;

 ENTITY entity_name
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

ENTITY entity_name IS
    PORT port_name
    ( signal_names : signal_modes signal_type;
    signal_names : signal_modes signal_type);
   END entity_name;

ENTITY entity_name
    PORT port_name
    (signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

ENTITY mux IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END mux;

ENTITY full_adder IS
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT (a ,b : IN BIT;
    s, c : OUT BIT);
    END full_adder;

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT (a, b, c, s, co : BIT);
    END full_adder;

ARCHITECTURE architecture_type OF entity_name IS
     Declarations_for_architecture;
     BEGIN
     Code;
     ….
    END architecture_name;

ARCHITECTURE architecture_name OF entity_name IS
     BEGIN
     Declarations_for_architecture;
     Code;
     ….
    END architecture_name;

ARCHITECTURE architecture_type OF entity_name IS
     BEGIN
     Declarations_for_architecture;
     Code;
     ….
    END architecture_type;

ARCHITECTURE architecture_name OF entity_name IS
     Declarations_for_architecture
     BEGIN
     Code;
     ….
     END architecture_name;

ARCHITECTURE my_arch OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END my_arch;

BEGIN
     ARCHITECTURE my_arch OF nand_gate IS
    x <= a NAND b;
    END behavioral;

BEGIN
    ARCHITECTURE behavioral OF nand_gate IS
    x <= a NAND b;
    END my_arch;

ARCHITECTURE nand OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END nand;

Up To Date Introduction to VHDL ( VHDL ) MCQs – VHDL MCQs