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Testing
1. Which of the following is a set of specially selected input patterns?
a) test pattern
b) debugger pattern
c) bit pattern
d) byte pattern
Answer: a
Explanation: While testing any devices or embedded systems, we apply some selected inputs which is known as the test pattern and observe the output. This output is compared with the expected output. The test patterns are normally applied to the already manufactured systems.
2. Which is applied to a manufactured system?
a) bit pattern
b) parity pattern
c) test pattern
d) byte pattern
Answer: c
Explanation: For testing any devices or embedded systems, we use some sort of selected inputs which is known as the test pattern and observe the output and is compared with the expected output. These test patterns are normally applied to the manufactured systems.
3. Which of the following is based on fault models?
a) alpha-numeric pattern
b) test pattern
c) bit pattern
d) parity pattern
Answer: b
Explanation: The test pattern generation is normally based on the fault models and this model is also known as the stuck-at model. The test pattern is based on a certain assumption, that is why it is called the stuck-at model.
4. Which is also called stuck-at model?
a) byte pattern
b) parity pattern
c) bit pattern
d) test pattern
Answer: d
Explanation: The test pattern generation is basically based on the fault models and this type of model is also known as the stuck-at model. These test patterns are based on a certain assumption, hence it is known as the stuck-at model.
5. How is the quality of the test pattern evaluated?
a) fault coverage
b) test pattern
c) size of the test pattern
d) number of errors
Answer: a
Explanation: The quality of the test pattern can be evaluated on the basis of the fault coverage. It is the percentage of potential faults that can be found for a given test pattern set, that is fault coverage equals the number of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.
6. What is DfT?
a) discrete Fourier transform
b) discrete for transaction
c) design for testability
d) design Fourier transform
Answer: c
Explanation: The design of testability or DfT is the process of designing for the better testability.
7. Which of the following is also known as boundary scan?
a) test pattern
b) JTAG
c) FSM
d) CRC
Answer: b
Explanation: The JTAG is a technique for connecting scan chains of several chips and is also known as boundary scan.
8. What does BILBO stand for?
a) built-in logic block observer
b) bounded input bounded output
c) built-in loading block observer
d) built-in local block observer
Answer: a
Explanation: The BILBO or the built-in logic block observer is proposed as a circuit combining, test response compaction, test pattern generation, and serial input/output capabilities.
9. What is CRC?
a) code reducing check
b) counter reducing check
c) counting redundancy check
d) cyclic redundancy check
Answer: d
Explanation: The CRC or the cyclic redundancy check is the error detecting code which is commonly used in the storage device and the digital networks.
10. What is FSM?
a) Fourier state machine
b) finite state machine
c) fast state machine
d) free state machine
Answer: b
Explanation: The FSM is the finite state machine. It will be having a finite number of states and is used to design both the sequential logic circuit and the computer programs. It can be used for testing the scan design in the testing techniques.
11. Which of the following have flip-flops which are connected to form shift registers?
a) scan design
b) test pattern
c) bit pattern
d) CRC
Answer: a
Explanation: All the flip-flop storing states are connected to form a shift register in the scan design. It is a kind of test path.
Risk and Dependability Analysis
1. Which is a top-down method of analyzing risks?
a) FTA
b) FMEA
c) Hazards
d) Damages
Answer: a
Explanation: The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.
2. What is FTA?
a) free tree analysis
b) fault tree analysis
c) fault top analysis
d) free top analysis
Answer: b
Explanation: The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.
3. Which gate is used in the geometrical representation, if a single event causes hazards?
a) AND
b) NOT
c) NAND
d) OR
Answer: d
Explanation: The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation if several events cause hazards.
4. Which analysis uses the graphical representation of hazards?
a) Power model
b) FTA
c) FMEA
d) First power model
Answer: b
Explanation: The FTA is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous.
5. Which gate is used in the graphical representation, if several events cause hazard?
a) OR
b) NOT
c) AND
d) NAND
Answer: c
Explanation: The fault tree analysis is done graphically by using gates. The main gates used are AND gates and OR gates. The AND gates are used in the graphical representation if several events cause hazards.
6. What is FMEA?
a) fast mode and effect analysis
b) front mode and effect analysis
c) false mode and effect analysis
d) failure mode and effect analysis
Answer: d
Explanation: The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.
7. Which of the following can compute the exact number of clock cycles required to run an application?
a) layout model
b) coarse-grained model
c) fine-grained model
d) register-transaction model
Answer: c
Explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.
8. Which model is capable of reflecting the bidirectional transfer of information?
a) switch-level model
b) gate level
c) layout model
d) circuit-level model
Answer: a
Explanation: The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of reflecting bidirectional transferring of the information.
Formal Verification
1. What is meant by FOL?
a) free order logic
b) fast order logic
c) false order logic
d) first order logic
Answer: d
Explanation: Many formal verification techniques are used and these are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The FOL is the abbreviated form of the first order logic which includes the quantification.
2. What is HOL?
a) higher order logic
b) higher order last
c) highly organised logic
d) higher order less
Answer: a
Explanation: The formal verification techniques are classified on the basis of the logics employed. The techniques are propositional logic, first order logic, and higher order logic. The HOL is the abbreviation of the higher order logic in which the proofs are automated and manually done with some proof support.
3. What is BDD?
a) boolean decision diagram
b) binary decision diagrams
c) binary decision device
d) binary device diagram
Answer: b
Explanation: The binary decision diagram is a kind of data structure which is used to represent the Boolean function.
4. Which formal verification technique consists of a Boolean formula?
a) HOL
b) FOL
c) Propositional logic
d) Both HOL and FOL
Answer: c
Explanation: The propositional logic technique is having the boolean formulas and the boolean function. The tools used in propositional logic is the tautology checker or the equivalence checker which in turn uses the binary decision diagrams which are also known as BDD.
5. Which of the following is also known as equivalence checker?
a) BDD
b) FOL
c) Tautology checker
d) HOL
Answer: c
Explanation: The propositional logic technique consists of the boolean formulas and the boolean function. The tools used in this type of logic is the tautology checker or the equivalence checker which in turn uses the BDD or the binary decision diagrams.
6. Which of the following is possible to locate errors in the specification of the future bus protocol?
a) EMC
b) HOL
c) BDD
d) FOL
Answer: c
Explanation: The model checking was developed using the binary decision diagram and the BDD and it was possible to locate errors in the specification of the future bus protocol.
7. Which of the following is a popular system for model checking?
a) HOL
b) FOL
c) BDD
d) EMC
Answer: d
Explanation: The EMC-system is developed by Clark and it describes the CTL formulas, which is the computational tree logics.
8. What is CTL?
a) computational tree logic
b) code tree logic
c) cpu tree logic
d) computer tree logic
Answer: a
Explanation: The EMC-system is a popular system for model checking which is developed by Clark that describes the CTL formulas, which is also known as computational tree logics. The CTL consist of two parts, a path quantifier, and a state quantifier.